Power Problems in VLSI Circuit Testing

Controlling or reducing power consumption during test and reducing test time are conflicting goals. Weighted random patterns (WRP) and transition density patterns (TDP) can be effectively deployed to reduce test length with higher fault coverage in scan-BIST circuits. New test pattern generators (TPG) are proposed to generate weighted random patterns and controlled transition density patterns to facilitate efficient scan-BIST implementations. We achieve reduction in test application time without sacrificing fault coverage while maintaining any given test power constrain by dynamically adapting the scan clock, accomplished by a built-in hardware monitor of transition density in the scan register.